The present invention relates to a semiconductor memory device, and in particular, to a circuit technique suitable for a high-speed and highly-integrated semiconductor memory device.
The semiconductor memory devices includes a dynamic random access memory (DRAM), a static random access memory (SRAM), and a pseudo SRAM. The DRAM is designed using a volatile dynamic memory cell architecture and includes cells each including a single transistor and a single capacitor. The DRAM is volatile, that is, when power source voltage thereof is interrupted, the data stored therein is lost. To continuously keep charge in the capacitor, it is required to periodically refresh the memory. The SRAM is inspected by use of a volatile static memory cell architecture. It is not required to refresh data stored in the memory. As long as power is supplied thereto, the data is kept therein for a long period of time. The pseudo SRAM is designed according to a single-transistor and single-capacitor memory cell architecture, not the volatile dynamic memory architecture used for the DRAM. It is therefore required to periodically refresh the pseudo SRAM.
A known example of the pseudo SRAM includes pseudo four-transistor memory cells. To refresh the memory cells, a refresh pulse is supplied to word lines during a precharge level period of paired data lines (reference is to be made to, for example, JP-A-10-501363 (PCT) (FIG. 3) corresponding to WO95/33265).
In another known example of the pseudo SRAM a rewrite cycle is concealed in the read•write operation as below. While a sense amplifier connected to a pair of bit lines is operating (or is precharging bit lines), an access transistor is slightly turned on (reference is to be made to, for example, JP-A-2001-202775 (FIG. 1; paragraph 20)).